mitsubishi semiconductor ps21265-p/ap transfer-mold type insulated type oct. 2005 ps21265 integrated power functions 600v/20a low-loss 5 th generation igbt inverter bridge for three phase dc-to-ac power conversion application ac100v~200v three-phase inverter drive for small power motor control. fig. 1 package outlines mitsubishi semiconductor ps21265-p/ap transfer-mold type insulated type integrated drive, protection and system control functions for upper-leg igbt s :drive circuit, high voltage high-speed level shifting, control supply under-voltage (uv) protection. for lower-leg igbt s : drive circuit, control supply under-voltage protection (uv), short circuit protection (sc). fault signaling : corresponding to an sc fault (lower-side igbt) or a uv fault (lower-side supply). ? nput interface : 3, 5v line compatible. (high active) ? l approved : yellow card no. e80276 dimensions in mm (short-pin type : ps21265-p) refer fig. 6 for long-pin type : PS21265-AP. terminal code 1. up 2. vp1 3. vufb 4. vufs 5. vp 6. vp1 7. vvfb 8. vvfs 9. wp 10. vp1 11. vpc 12. vwfb 13. vwfs 14. vn1 15. vnc 16. cin 17. cfo 18. fo 19. un 20. vn 21. wn 22. p 23. u 24. v 25. w 26. n note t ype name , lot no. 26 25 24 23 22 1 irregular solder remains irregular solder remains 1 0.2 0.6 0.5 0.5max c0.2 c0.2 (2.5) 0.8 0.2 (0 ~ 5 ) 1 0.2 0.7 0.2 0.7 0.2 0.6 0.5 0.8 0.2 0.45 0.2 0.45 0.2 0.8 0.2 0.45 0.2 0.5max c b 8 0.5 heat sink side terminal 22, 26 o thers o thers detail b (5 pins t = 0.7) detail c (21 pins t = 0.7) terminal 1-2, 20-21 heat sink side 12.8 0.5 2 3 4 5 6 7 8 9 10 13 12 15 14 16 17 18 19 20 21 11 20 0.3 10 0.3 10 0.3 10 0.3 79 0.5 (71) 67 0.3 2- 4.5 0.2 2.8 0.3 27 2.8(=75.6) 11.5 0.5 31 0.5 (11.5) (8.5) 28 0.5 0.5 0.2 detail d detail a d 21.4 0.5 13.4 0.5 34.9 0.5 3.8 0.2 a note: all outer lead terminals are with pb-free solder plating. free datasheet http:///
mitsubishi semiconductor ps21265-p/ap transfer-mold type insulated type oct. 2005 note1: in the recommended external protection circuit, please select the rc time constant in the range 1.5~2.0 s. 2: to prevent erroneous protection operation, the wiring of a, b, c should be as short as possible. drive circuit drive circuit protection circuit w v u b c v nc cin a p n1 n c r shunt resistor external protection circuit dip-ipm l-side igbt s h-side igbt s sc protection trip level i c (a) t w ( s) 2 0 short circuit protective function (sc) : sc protection is achieved by sensing the l-side dc-bus current (through the external shunt resistor) after allowing a suitable filtering time (defined by the rc circuit). when the sensed shunt voltage exceeds the sc trip-level, all the l-side igbts are turned off and a fault signal (fo) is output. since the sc fault may be repetitive, it is recommended to stop the system when the fo signal is received and check the fault. collector current waveform (note 1) (note 2) cin ac line input drive circuit cbu cbu+ cbv cbv+ cbw cbw+ (15v line) (3, 5v line) (note 1, 2) v d v nc w v u input signal conditioning level shifter drive circuit protection circuit (uv) input signal conditioning input signal conditioning input signal conditioning fo logic protection circuit circuit (uv) protection circuit (uv) control supply under-voltage protection drive circuit drive circuit f o cfo p n1 n fault output (5v line) (note 3, 5) high-side input (pwm) (3, 5v line) (note 1, 2) low-side input (pwm) (note 6) (note 7) (note 7) dip-ipm z : znr (surge absorber) c : ac filter (ceramic capacitor 2.2~6.5nf) (note : additionally, an appropriate line-to line surge absorber circuit may become necessary depending on the application environment.) c2 c1 c1 : tight tolerance, temp-compensated electrolytic type c2 : 0.22~2 f r-category ceramic capacitor for noise filtering (note : the capacitance value depends on the pwm control scheme used in the applied system.) note1: the logic of input signal is high-active. the dip-ipm input signal section integrates a 2.5k ? (min) pull-down resistor. if using external rc filter, pay attention to satisfy the turn-on/off threshold voltage requirement. 2: by virtue of integrating an application specific type hvic inside the module, direct coupling to mcu terminals without any opto-coupler or transformer isolation is possible. 3: this output is open drain type. the signal line should be pulled up to the positive side of the 5v power supply with appro ximately 10k ? resistor. 4: the wiring between the power dc link capacitor and the p, n1 terminals should be as short as possible to protect the dip-ip m against catastrophic high surge voltages. for extra precaution, a small film type snubber capacitor (0.1~0.22 f, high voltage type) is recommended to be mounted close to these p & n1 dc power input pins. 5: fo output pulse width should be decided by putting external capacitor between cfo and v nc terminals. (example : c fo =22nf t fo =1.8ms (typ.)) 6: high voltage (600v or more) and fast recovery type (less than 100ns) diodes should be used in the bootstrap circuit. 7: to prevent ic s from surge destruction, it is recommended to insert a zener diode (24v, 1w) between each control supply terminals. h-side igbt s l-side igbt s (note 4) inrush current limiter circuit level shifter level shifter protection ac line output m v nc z c fig. 2 internal functions block diagram (typical application example) fig. 3 external part of the dip-ipm protection circuit free datasheet http:///
mitsubishi semiconductor ps21265-p/ap transfer-mold type insulated type oct. 2005 note 2 : t c measurement point power terminals heat sink boundary heat sink control terminals t c t c 400 ?0~+100 ?0~+125 2500 v d = 13.5~16.5v, inverter part t j = 125 c, non-repetitive, less than 2 s (note 2) 60hz, sinusoidal, ac 1 minute, connecting pins to heat-sink plate v cc(prot) t c t stg v iso v v v v ma v 20 20 ?.5~v d +0.5 ?.5~v d +0.5 1 ?.5~v d +0.5 applied between v p1 -v pc , v n1 -v nc applied between v ufb -v ufs , v vfb -v vfs , v wfb -v wfs applied between u p , v p , w p -v pc , u n , v n , w n -v nc applied between f o -v nc sink current at f o terminal applied between cin-v nc control supply voltage control supply voltage input voltage fault output supply voltage fault output current current sensing input voltage v d v db v in v fo i fo v sc 450 500 600 20 40 51.2 ?0~+125 applied between p-n applied between p-n t c = 25 c t c = 25 c, less than 1ms t c = 25 c, per 1 chip (note 1) v cc v cc(surge) v ces i c i cp p c t j condition symbol parameter ratings unit supply voltage supply voltage (surge) collector-emitter voltage each igbt collector current each igbt collector current (peak) collector dissipation junction temperature v v v a a w c maximum ratings (t j = 25 c, unless otherwise noted) inverter part condition symbol parameter ratings unit control (protection) part symbol ratings unit self protection supply voltage limit (short circuit protection capability) module case operation temperature storage temperature isolation voltage v c c v rms to ta l system note 1 : the maximum junction temperature rating of the power chips integrated within the dip-ipm is 150 c (@ t c 100 c) however, to in- sure safe operation of the dip-ipm, the average junction temperature should be limited to t j(ave) 125 c (@ t c 100 c). parameter condition free datasheet http:///
mitsubishi semiconductor ps21265-p/ap transfer-mold type insulated type oct. 2005 2.05 2.15 2.00 1.85 0.60 2.10 0.80 1 10 1.95 3.00 0.067 ma v t j = 25 c t j = 125 c i c = 20a, t j = 25 c i c = 20a, t j = 125 c v ce(sat) v ec t on t rr t c(on) t off t c(off) i ces condition symbol parameter limits inverter igbt part (per 1/6 module) inverter fwdi part (per 1/6 module) case to fin (per 1 module) thermal grease applied r th(j-c)q r th(j-c)f r th(c-f)f min. thermal resistance t yp. max. unit t j = 25 c, ? c = 20a, v in = 0v condition symbol parameter limits min. t yp. max. 0.65 unit electrical characteristics (t j = 25 c, unless otherwise noted) inverter part collector-emitter saturation voltage fwdi forward voltage junction to case thermal resistance (note 3) v d = v db = 15v v in = 5v switching times v cc = 300v, v d = v db = 15v i c = 20a, t j = 125 c, v in = 0 ? 5v inductive load (upper-lower arm) collector-emitter cut-off current v ce = v ces 1.55 1.65 1.50 1.25 0.30 0.40 1.50 0.50 v s s s s s c/w c/w c/w control (protection) part note 4 : short circuit protection is functioning only at the low-arms. please select the external shunt resistance such that the sc trip -level is less than 2.0 times of the collector current rating (20a). 5: fault signal is output when the low-arms short circuit or control supply under-voltage protective functions operate. the fault output pulse- width t fo depends on the capacitance value of c fo according to the following approximate equation : c fo = 12.2 ? 10 -6 ? t fo [f]. symbol i d v foh v fol v sc(ref) i in uv dbt uv dbr uv dt uv dr t fo v th(on) v th(off) parameter condition limits unit circuit current fault output voltage short circuit trip level control supply under-voltage protection fault output pulse width on threshold voltage off threshold voltage v d = v db = 15v v in = 5v t otal of v p1 -v pc , v n1 -v nc v ufb -v ufs , v vfb -v vfs , v wfb -v wfs v sc = 0v, f o circuit pull-up to 5v with 10k ? v sc = 1v, i fo = 1ma t c = ?0~100 c, v d = 15v (note 4) v in = 5v t rip level reset level t rip level reset level c fo = 22nf (note 5) applied between u p , v p , w p -v pc , u n , v n , w n -v nc 4.9 0.45 1.0 10.0 10.5 10.3 10.8 1.0 2.1 0.8 1.5 1.8 2.3 1.4 7.00 0.55 7.00 0.55 0.95 0.52 2.0 12.0 12.5 12.5 13.0 2.6 2.1 min. typ. max. ma ma ma ma v v v ma v v v v ms v v v d = v db = 15v v in = 0v t otal of v p1 -v pc , v n1 -v nc v ufb -v ufs , v vfb -v vfs , v wfb -v wfs t j 125 c note 3 : grease with good thermal conductivity should be applied evenly with a thickness of about +100 m~+200 m on the contact surface of dip-ipm and heat-sink. input current contact thermal resistance free datasheet http:///
mitsubishi semiconductor ps21265-p/ap transfer-mold type insulated type oct. 2005 note 6 : + + measurement point heat sink heat sink 3mm place to contact a heat sink mounting screw : m4 condition parameter limits mounting torque w eight heat-sink flatness min. mechanical characteristics and ratings t yp. max. 0.98 ?0 unit 54 1.47 100 n? g m recommended : 1.18 n? ( note 6 ) v v v v/ s s khz arms s v supply voltage control supply voltage control supply voltage control supply variation arm shoot-through blocking time pwm input frequency allowable r.m.s. current minimum input pulse width v nc variation applied between p-n applied between v p1 -v pc , v n1 -v nc applied between v ufb -v ufs , v vfb -v vfs , v wfb -v wfs for each input signal, t c 100 c t c 100 c, t j 125 c v cc = 300v, v d = v db = 15v, p .f = 0.8, sinusoidal pwm t c 100 c, t j 125 c (note 7) (note 8) 200 v cc 350v, 13.5 v d 16.5v, 13.0 v db 18.5v, ?0 c t c 100 c, n-line wiring inductance less than 10nh (note 9) between v nc -n (including surge) 400 16.5 18.5 1 20 14.0 9.5 5.0 v cc v d v db ? v d , ? v db t dead f pwm i o pwin(on) pwin(off) v nc condition symbol parameter recommended value min. t yp. max. 0 13.5 13.0 ? 2 0.3 1.4 2.5 3.0 ?.0 unit recommended operation conditions 300 15.0 15.0 note 7 : the allowable r.m.s. current value depends on the actual application conditions. 8: input signal with on pulse width less than pwin(on) might make no response. 9: ipm might make no response or response delay to next turn-on pulse if off-pulse width is less than pwin(off). (please refer to fig. 4) please refer to fig. 9 for recommended wiring method too. f pwm = 5khz f pwm = 15khz below rated current between rated current and 1.7 times of rated current between 1.7 times and 2.0 times of rated current free datasheet http:///
mitsubishi semiconductor ps21265-p/ap transfer-mold type insulated type oct. 2005 fig. 4 current output when input signal is less than allowable minimum input pulse width pwin(off) (p-side only) dip-ipm u out v out w out v no cfo gnd fo w n v n u n v cc hvic3 hvic2 hvic1 lvic cfo cin cin n w v u p ho in com v b v s v cc ho in com v b v s v cc ho in com v b v s v cc fo w n v n u n w p v p u p v nc v n1 v p1 v p1 v p1 v wfs v vfs v ufs v wfb v vfb v ufb igbt1 igbt2 igbt3 igbt4 igbt5 igbt6 di1 di2 di3 di4 di5 di6 v pc fig. 5 the dip-ipm internal circuit t1 t2 real line ... off pulse width > pwin(off) ; turn on time t1 broken line ... off pulse width < pwin(off) ; turn on time t2 p-side control input internal igbt gate output current ic free datasheet http:///
mitsubishi semiconductor ps21265-p/ap transfer-mold type insulated type oct. 2005 fig. 6 package outlines (long-pin type : PS21265-AP) irregular solder remains irregular solder remains 1 0.2 (0.7) (1) 0.6 0.5 0.5max c0.2 c0.2 (2.5) 0.8 0.2 (0.6) 1 0.2 0.7 0.2 0.7 0.2 0.6 0.5 0.8 0.2 0.45 0.2 0.45 0.2 0.8 0.2 0.45 0.2 (1) 0.5max t ype name , lot no. 26 25 24 23 22 1 (0 ~ 5 ) c b 8 0.5 heat sink side terminal 22, 26 o thers o thers detail b (5 pins t = 0.7) detail c (21 pins t = 0.7) terminal 1-2, 20-21 heat sink side 16 0.5 2 3 4 5 6 7 8 9 10 13 12 15 14 16 17 18 19 20 21 11 79 0.5 (71) 67 0.3 2- 4.5 0.2 2.8 0.3 27 2.8(=75.6) 11.5 0.5 31 0.5 (11.5) (8.5) 28 0.5 0.5 0.2 detail d detail a d 21.4 0.5 13.4 0.5 3.8 0.2 a terminal code 1. up 2. vp1 3. vufb 4. vufs 5. vp 6. vp1 7. vvfb 8. vvfs 9. wp 10. vp1 11. vpc 12. vwfb 13. vwfs 14. vn1 15. vnc 16. cin 17. cfo 18. fo 19. un 20. vn 21. wn 22. p 23. u 24. v 25. w 26. n 20 0.3 10 0.3 10 0.3 10 0.3 note 35 0.6 note: all outer lead terminals are with pb-free solder plating. free datasheet http:///
mitsubishi semiconductor ps21265-p/ap transfer-mold type insulated type oct. 2005 error output fo output current ic control supply voltage v d protection circuit state control input b1 b2 b3 b4 b5 reset reset uv dt uv dr set b6 b7 protection circuit state lower-arms control input error output fo sense voltage of the shunt resistance output current ic internal igbt gate sc reference voltage cr circuit time constant delay a5 a8 a4 a3 a1 a2 sc reset set a7 a6 fig. 7 timing charts of the dip-ipm protective functions [a] short-circuit protection (lower-arms only) (with external shunt resistor and cr connection) a1. normal operation : igbt on and carrying current. a2. short circuit current detection (sc trigger). a3. hard igbt gate interrupt. a4. igbt turns off. a5. f o timer operation starts : the pulse width of the f o signal is set by the external capacitor c fo . a6. input ??: igbt off state. a7. input ??: igbt on state, but during the f o signal active period the igbt doesn? turn on. a8. igbt off in spite of ??input. [b] under-voltage protection (lower-arm, uv d ) b1. control supply voltage rises : after the voltage reaches uv dr level, the circuits start to operate when the next input is applied. b2. normal operation : igbt on and carrying current. b3. under voltage trip (uv dt ). b4. igbt off in spite of control input condition. b5. f o operation starts. the minimum pulse width of f o is set by the external capacitor c fo , and f o outputs continuously during uv period. b6. under voltage reset (uv dr ). b7. normal operation : igbt on and carrying current. free datasheet http:///
mitsubishi semiconductor ps21265-p/ap transfer-mold type insulated type oct. 2005 mcu 10k ? u p ,v p ,w p ,u n ,v n ,w n v nc (logic) fo dip-ipm 5v line [c] under-voltage protection (upper-arm, uv db ) c1. control supply voltage rises : operation starts soon after uv dbr . c2. normal operation : igbt on and carrying current. c3. under voltage trip (uv dbt ). c4. igbt off in spite of control input condition, but there is no f o signal output. c5. under voltage reset (uv dbr ). c6. normal operation : igbt on and carrying current. fig. 8 recommended mcu i/o interface circuit note : rc coupling at each input (parts shown dotted) might change depending on the pwm control scheme used in the application and the wiring impedance of the application s printed circuit board. the dip-ipm input signal section integrates a 2.5k ? (min) pull-down resistor. therefore, if using external rc filter, pay attention to satisfy the turn-on/off threshold voltage requirement. fig. 9 recommended wiring of shunt resistor v nc n dip-ipm wiring inductance should be less than 10nh. shunt resistor width=3mm, thickness=100 m, length=17mm in copper pattern (rough standard) please make the connection point as close as possible to the terminal of shunt resistor. control input protection circuit state control supply voltage v db output current ic error output fo high-level (no fault output) uv dbr reset set reset uv dbt c1 c3 c4 c5 c6 c7 c2 free datasheet http:///
mitsubishi semiconductor ps21265-p/ap transfer-mold type insulated type oct. 2005 fig. 10 example of typical dip-ipm application circuit note 1 : to prevent the input signals oscillation, the wiring of each input should be as short as possible. (less than 2-3cm) 2: by virtue of integrating an application specific type hvic inside the module, direct coupling to mcu terminals without any opto -coupler or transformer isolation is possible. 3: f o output is open drain type. this signal line should be pulled up to the positive side of the 5v power supply with approximately 10k ? resistor. 4: f o output pulse width is determined by the external capacitor between cfo and v nc terminals (c fo ). (example : c fo = 22nf t fo = 1.8ms (typ.)) 5: the logic of input signal is high-active. the dip-ipm input signal section integrates a 2.5k ? (min) pull-down resistor. if using external rc filter, pay attention to satisfy the turn-on/off threshold voltage requirement. 6: to prevent malfunction of protection, the wiring of a, b, c should be as short as possible. 7: please set the r1c5 time constant in the range 1.5~2 s. 8: each capacitor should be located as nearby the pins of the dip-ipm as possible. 9: to prevent surge destruction, the wiring between the smoothing capacitor and the p, n1 pins should be as short as possible. app roxi- mately a 0.1~0.22 f snubber capacitor between the p-n1 pins is recommended. 10 : to prevent ic s from surge destruction, it is recommended to insert a zener diode (24v, 1w) between each control supply terminals. ho ho dip-ipm c3 c3 c3 c2 c2 c2 c1 c1 c1 ho in in 15v line 5v line in com com com u out v out w out v no cfo gnd f o w n v n v cc c b a c4(c fo ) cfo r1 n1 c5 cin cin n w v u p v s v s v s v b v b v b v cc v cc v cc fo w n v n u n u n w p v p u p v nc v n1 v p1 v pc v p1 v p1 v wfs v vfs v ufs v wfb v vfb v ufb m c3 controller hvic1 hvic2 hvic3 lvic c1:tight tolerance temp-compensated electrolytic type (note: the capacitance value depends on the pwm control used in the applied system.) c2,c3: 0.22 ~ 2 f r-category ceramic capacitor for noise filtering. if this wiring is too long, short circuit might be caused. shunt resistor if this wiring is too long, the sc level fluctuation might be larger and cause sc malfunction. the long wiring of gnd might generate noise on input and cause igbt to be malfunction. free datasheet http:///
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